Static random access memory timing tracking circuit
US8958237B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.