Logic-based multiple time programming memory cell compatible with generic CMOS processes
US8958245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.