Semiconductor memory device
US8958247B2 · kind B2 · utility
26Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Aug 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.