High performance two-port SRAM architecture using 8T high performance single port bit cell
US8958254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Feb 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.