Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus
US8959380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | May 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.