Considering compatibility of adjacent boundary regions for standard cells placement and routing
US8959472B1 · kind B1 · utility
21Cited by
10References
16Claims
0Family size
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Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Sep 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.