Patent · US Active

Complementary stress memorization technique layer method

US8962419B2 · kind B2 · utility

2Cited by

3References

10Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Russell Carlton McMullan · Austin, US
Dong-Joo Bae · Plano, US

Key dates

Filing date	Sep 26, 2014
Grant date	Feb 24, 2015
Priority date	—
Expiry date	Sep 26, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/0212
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.