Chip-on-wafer structures and methods for forming the same
US8962481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2014 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jan 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.