Simultaneous isolation trench and handle wafer contact formation
US8963281B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.