Semiconductor chip with seal ring and sacrificial corner pattern
US8963291B2 · kind B2 · utility
3Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2011 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.