Patent · US Active

Stacked multi-chip integrated circuit package

US8963339B2 · kind B2 · utility

55Cited by

5References

28Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Dongming He · Gilbert, US
Zhongping Bao · San Diego, US
Zhenyu Huang · Shanghai, CN

Key dates

Filing date	Oct 8, 2012
Grant date	Feb 24, 2015
Priority date	—
Expiry date	Feb 27, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/35121
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.