Ferroelectric memories with a stress buffer
US8963343B1 · kind B1 · utility
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12References
15Claims
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Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Sep 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device including a ferroelectric memory and methods of manufacturing the same are provided. In one embodiment, the device includes a semiconductor die with an integrated circuit fabricated thereon, a stress buffer die mounted to the semiconductor die overlying the integrated circuit, and a molding compound encapsulating the semiconductor die and the stress buffer die. Generally the integrated circuit includes a ferroelectric memory. In some embodiments, the device further includes a polyimide layer between the stress buffer and the semiconductor die. Other embodiments are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.