Tiling compaction in multi-processor systems
US8963931B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2010 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for processing a graphics frame in a multi-processor computing environment are described. Embodiments of the present invention enable the reduction of the memory footprint required for processing a graphics frame in a multi-processor system. In one embodiment a method of processing a graphics frame using a plurality of processors is presented. The method includes determining a respective assignment of tiles of the graphics frame to each processor of the plurality of processors; allocating a memory area in a local memory of each processor, where the size of the allocated memory area substantially corresponds to the aggregate size of tiles assigned to the respective processor; and storing the tiles of the respective assignment of tiles in the memory area of each respective processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.