Fast parallel test of SRAM arrays
US8966329B2 · kind B2 · utility
9Cited by
6References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2011 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jan 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, each parallel test operation on Static Random Access Memory (SRAM) cells is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.