Array substrate and manufacturing method thereof
US8969146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | May 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.