Methods of fabricating semiconductor devices using double patterning technology
US8969215B2 · kind B2 · utility
4Cited by
5References
13Claims
0Family size
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Key dates
| Filing date | Nov 13, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.