Single poly plate low on resistance extended drain metal oxide semiconductor device
US8969962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Aug 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.