Patent · US Active

Bonded stacked wafers and methods of electroplating bonded stacked wafers

US8970043B2 · kind B2 · utility

0Cited by

8References

16Claims

0Family size

Assignee

Maxim Integrated Products, Inc. · US

Inventors

Quanbo Zou · Pleasanton, US
Uppili Sridhar · Singapore, SG
Amit S. Kelkar · Flower Mound, US
Xuejun Ying · San Jose, US

Key dates

Filing date	Feb 1, 2011
Grant date	Mar 3, 2015
Priority date	—
Expiry date	Nov 18, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/30101
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.