Process compensated delay line
US8970275B1 · kind B1 · utility
3Cited by
13References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2008 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Jun 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.