Erase operations with erase-verify voltages based on where in the erase operations an erase cycle occurs
US8971125B2 · kind B2 · utility
4Cited by
8References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Jul 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods of erasing the memory devices are disclosed. One such method includes performing an erase cycle of an erase operation on a plurality of memory cells, where performing the erase cycle of the erase operation includes selecting an erase verify voltage to be applied during the erase cycle from a plurality of erase verify voltages based on where in the erase operation the erase cycle occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.