Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time reference
US8972767B2 · kind B2 · utility
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6References
17Claims
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Key dates
| Filing date | Nov 16, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.