Integrated circuits capable of generating test mode control signals for scan tests

US8972807B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Rajesh Mittal · Bengaluru, IN
• Puneet Sabbarwal · Bengaluru, IN
• Prakash Narayanan · Bengaluru, IN
• Rubin Ajit Parekhji · Bengaluru, IN

Key dates

• Filing date: May 14, 2012
• Grant date: Mar 3, 2015
• Expiry date: Jun 22, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.