High speed interconnect protocol and method
US8972828B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Sep 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of error mitigation for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method including grouping a pre-selected number of high speed interconnect protocol words to form a protection frame, adding at least one additional error protection bit to each word in the group, adding a synchronization bit to each word, using the synchronization bit in a first word in each frame for synchronization of the protection frame and detecting and correcting a single bit error in the protection frame using the additional error protection bits, thereby reducing packet drop when the frames are transferred over the high speed data interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.