Encoding and decoding of information using a block code matrix
US8972835B1 · kind B1 · utility
13Cited by
20References
14Claims
0Family size
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Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Jan 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n−1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n−1) parity bits to generate an (n) parity bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.