Method of creating a maskless air gap in back end interconnects with double self-aligned vias

US8975138B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Manish Chandhok · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Yan Borodovsky · Portland, US
• Florian Gstrein · Portland, US
• David Shykind · Buxton, US
• Kevin Lin · Beaverton, US

Key dates

• Filing date: Jun 28, 2013
• Grant date: Mar 10, 2015
• Expiry date: Jun 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.