Patent · US Active

Integrated circuit packaging system with coreless substrate and method of manufacture thereof

US8975665B2 · kind B2 · utility

2Cited by
2References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 16, 2013
Grant dateMar 10, 2015
Priority date—
Expiry dateJan 16, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15311
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.