Patent · US Active

Store buffer for transactional memory

US8977823B2 · kind B2 · utility

3Cited by
1References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 16, 2012
Grant dateMar 10, 2015
Priority date
Expiry dateApr 5, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F9/467
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.