Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

US8977835B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Maarten J. Boersma · Holzgerlingen, DE
• Markus Kaltenbach · Holzgerlingen, DE
• Christophe J. Layer · Eppelheim, DE
• Jens Leenstra · Nagold, DE
• Silvia M. Mueller · Altdorf, DE

Key dates

• Filing date: Nov 14, 2013
• Grant date: Mar 10, 2015
• Expiry date: Nov 14, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/8053
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.