DRAM address protection
US8977944B2 · kind B2 · utility
4Cited by
4References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.