Timing budgeting of nested partitions for hierarchical integrated circuit designs
US8977995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2012 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.