Inventor · Noida, IN

Sushobhit Singh

9Patents

3h-index

15Co-inventors

50Inventor score

Filing activity: Jun 1, 2012 → Aug 29, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8572532B1	Common path pessimism removal for hierarchical timing analysis	Physics	35	Active
US8769455B1	Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs	Physics	25	Active
US8977995B1	Timing budgeting of nested partitions for hierarchical integrated circuit designs	Physics	25	Active
US10783300B1	Systems and methods for extracting hierarchical path exception timing models	Physics	1	Active
US10733346B1	Systems and methods for arc-based debugging in an electronic design	Physics	1	Active
US11455450B1	System and method for performing sign-off timing analysis of electronic circuit designs	Physics	1	Active
US9053270B1	Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs	Physics	0	Active
US12332304B1	System and method for automatic fault detection in an electronic design	Physics	0	Active
US11347915B1	System and method for objective probing and generation of timing constraints associated with an electronic circuit design	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.