Combinatorial optimization of interlayer parameters
US8980653B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Jul 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/694
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.