Semiconductor device and method of forming low profile 3D fan-out package
US8980691B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Jun 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.