Multi chip package
US8981549B2 · kind B2 · utility
3Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Aug 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.