Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment
US8981813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Jan 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.