Memory devices, circuits and, methods that apply different electrical conditions in access operations
US8982602B2 · kind B2 · utility
3Cited by
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22Claims
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Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.