Memory erasing method and driving circuit thereof
US8982641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.