DRAM sub-array level refresh
US8982654B2 · kind B2 · utility
8Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Nov 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.