Data space arbiter
US8984198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2010 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Oct 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.