Memory access control module and associated methods
US8984203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2012 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | May 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.