On-chip electrostatic discharge protection for a semiconductor device
US8987778B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
Embodiments of the invention provide increased ESD protection suitable for high-voltage devices. In one embodiment, an internal DMOS circuit is placed in parallel with a lateral NPN ESD clamp. The clamp has both a high holding voltage, above the operating voltage of the DMOS circuit, and a high maximum current before breakdown. The discharge path of the clamp includes a high-voltage lightly doped well containing a low-voltage higher doped well. The dopant of both wells is the same type, and the interface between the two defines a graded junction. The emitter of the entire circuit is grounded and the collector is coupled to the voltage of the DMOS circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.