State retention power gated cell
US8987786B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2014 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | May 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/65
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.