Semiconductor structure and method for manufacturing the same
US8987787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Apr 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.