Wafer and method of manufacturing the same
US8987867B2 · kind B2 · utility
2Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.