Circuit for generating a clock signal for interleaved PFC stages and method thereof
US8988048B2 · kind B2 · utility
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10References
11Claims
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Key dates
| Filing date | Apr 28, 2009 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.