Coarse gating of clock tree elements
US8988108B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.