Integrated antenna for RFIC package applications
US8988299B2 · kind B2 · utility
141Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2011 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15321
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A chip package includes a plurality of layers including conductive planes connected by vias. The layers include a first portion having an antenna formed therein and a parallel-plate mode suppression mechanism to suppress parallel-plate mode excitation of the antenna. The parallel-plate mode suppression mechanism includes a reflector offset from an antenna ground plane and first grounded vias. A second portion has an interface for connecting to an integrated circuit device wherein the first portion and the second portion are separated by the parallel-plate mode suppression mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.