Memory device and method of performing a read operation within such a memory device
US8988954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.