Consolidating multiple neurosynaptic cores into one memory

US8990130B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rodrigo Alvarez-Icaza Rivera · San Jose, US
• John V. Arthur · Mountain View, US
• Andrew S. Cassidy · San Jose, US
• Paul A. Merolla · Palo Alto, US
• Dharmendra S. Modha · San Jose, US

Key dates

• Filing date: Nov 21, 2012
• Grant date: Mar 24, 2015
• Expiry date: Jun 28, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/063
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention relate to a neural network system comprising a single memory block for multiple neurosynaptic core modules. One embodiment comprises a neural network system including a memory array that maintains information for multiple neurosynaptic core modules. Each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit. Each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module.