Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes
US8990607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.